What is the minimum pulse width required for the Arria 10 EMIF IP global_reset_n signal ? - What is the minimum pulse width required for the Arria 10 EMIF IP global_reset_n signal ?
Description The minimum reset pulse width requirement is 100ns.
Custom Fields values:
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Troubleshooting
FB: 480925;
False
['External Memory Interfaces Arria® 10 FPGA IP']
['FPGA Dev Tools Quartus® Prime Software Pro']
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16.0
['Arria® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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