* Error: Module parameter 'CFG_CMD_GEN_OUTPUT_REG' not found for override at alt_mem_ddrx_controller.v - * Error: Module parameter 'CFG_CMD_GEN_OUTPUT_REG' not found for override at alt_mem_ddrx_controller.v Description You might see the above error when simulating your DDR3 UniPHY controller with the ModelSim-Intel® FPGA. The cause of the error is the ordering of the compilation libraries in the ModelSim vsim elaboration call. Resolution You must make sure the library containing the DDR3 compiled files is listed first in the command. In this case, the work directory contains the DDR3 compiled files: vsim -novopt -t ps -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L altera_mf -L altera_lnsim -L stratixiv <top_level_filename> It is recommended that you follow the file and library ordering in the msim_setup.tcl file provided in the <IP_variation_name>_sim/mentor directory. Custom Fields values: ['novalue'] Troubleshooting 2205810055 False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] 14.0 13.0 ['Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']