Why does the F-Tile Triple-Speed Ethernet FPGA IP Design Example enable RX auto adaptation? - Why does the F-Tile Triple-Speed Ethernet FPGA IP Design Example enable RX auto adaptation? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, RX auto adaptation is enabled automatically in the design example generated by the F-Tile Triple-Speed Ethernet FPGA IP. According to AN 969: F-Tile PMA Tuning Guidelines , the following are the guidelines for RX auto adaptation: "For lower data rate applications which usually use unscrambled data, for example CPRI 6 Gbps and lower, DisplayPort less than 8 Gbps, you can disable auto adaptation. This is because, for these unscrambled data applications, DFE may have a challenge to converge and thus introduce errors or may result in performance degradation if auto adaptation is ON." Resolution To work around this problem, modify the Quartus® Settings File ( .qsf ) file of the generated design example to bypass RX auto adaptation according to “FGT PMA Settings” section on F-Tile Architecture and PMA and FEC Direct PHY IP User Guide . This problem has been fixed starting in version 24.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15014904585 False ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']