Incorrect TrustZone Information in SoC Technical Reference Manual - Incorrect TrustZone Information in SoC Technical Reference Manual Description The Arria V Device Handbook and Arria V Device Handbook contain incorrect information about the TrustZone security level for the transactions initiated by the Ethernet MAC and ETR master interfaces. The Interconnect chapter of Volume 3: Hard Processor System Technical Reference Manual in these handbooks incorrectly indicates that these transactions are nonsecure. Resolution The following table lists the correct TrustZone security levels for transactions from these component’s masters. Interconnect Master Interface Masters TrustZone Security EMAC 0/1 Secure ETR Per Transaction Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.0 12.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']