Why does the F-tile Serial Lite IV IP design with PAM4 modulation fail to achieve link up during simulation? - Why does the F-tile Serial Lite IV IP design with PAM4 modulation fail to achieve link up during simulation? Description Due to a problem in the Quartus® Prime Pro Edition software 24.2 and earlier versions, you might observe the F-tile Serial Lite IV Intel FPGA IP design with PAM4 modulation fail to get the rx_link_up asserted in simulation. This is because rx_cdr_lock is not asserted, which results in rx_pcs_ready not being asserted. This failure is caused by misinterpreting the AIB master and slave, introducing a deskew error in serial data in the soft reset controller. Resolution There is no workaround available. This problem only exists in simulation and does not impact the hardware testing results. This problem might disappear when you re-run the simulation. This is because the simulator might support random seed generation, and some seeds will not encounter this failure. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.3.1. Custom Fields values: ['novalue'] Troubleshooting 14022685084 False ['F-Tile Serial Lite IV IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']