Stratix V Hard IP for PCI Express IP Core Fails To Log First Error Pointer for Completion Timeout Error - Stratix V Hard IP for PCI Express IP Core Fails To Log First Error Pointer for Completion Timeout Error Description The Stratix V Hard IP for PCI Express IP Core logs Completion Timeout errors in the Uncorrectable Error Status register, but does not log Completion Timeout errors in the Advanced Error Reporting (AER) Header Log Register or First Error Pointer field of the Advanced Error Capabilities and Control register as described in Section 7.10.7 of the PCI Express Base Specification Rev. 3.0 . Resolution No workaround is available. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']