How do I view the row clock region boundaries in the Intel® Quartus® Prime Pro Edition Software? - How do I view the row clock region boundaries in the Intel® Quartus® Prime Pro Edition Software? Description The Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration says, "You cannot share a row clock between two PR regions" but it does not clearly specify how to view the row clock region boundaries in Intel® Quartus® Prime Pro Edition Software version. Resolution For Intel® Arria® 10 devices and Intel® Cyclone® 10 GX devices, follow these steps: Click Tools > Chip Planner. In Chip Planner, click the Layers tab and select the Basic layer . Check Spine Clock Region; you will see the spine clock region boundaries . A row clock region is half-spine clock wide (divided by the dotted line) and one LAB row tall. For Intel® Stratix® 10 devices and Intel Agilex® devices, follow these steps: Click Tools > Chip Planner . In Chip Planner, click the Layers tab and select the Basic layer . Check Clock Sector Region; you will see the clock sector region boundaries. A row clock region is half-clock sector-wide (divided by the dotted line) and one LAB row tall. Custom Fields values: ['novalue'] Troubleshooting 15010243047 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 21.3 ['Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']