Timing Issues with HDMI TX Core - Timing Issues with HDMI TX Core Description When you configure the HDMI TX core at 2 symbols per clock, your design may fail setup timing in every one out of ten Fitter seeds, with less than 100-ps negative slack. This issue specifically affects designs using Arria 10 GX and Stratix V GX devices.The critical path resides within the Transition Minimized Differential Signaling (TMDS) encoder. Resolution To work around this issue, turn on the Aggressive Performance Optimization mode in the Quartus Compiler Settings to achieve timing closure. This issue is fixed in version 15.1 Update 1 of the HDMI IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 15.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']