Why do I encounter discrepancy in CA Parity injection and detection in Agilex™ 7 FPGA EMIF IP example design using Quartus® Prime Pro Edition Software version 23.3? - Why do I encounter discrepancy in CA Parity injection and detection in Agilex™ 7 FPGA EMIF IP example design using Quartus® Prime Pro Edition Software version 23.3? Description Due to a problem in Quartus® Prime Pro Edition Software version 23.4, you might encounter an error in the CA Parity register not getting updated after error injection. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14020276300 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] 23.3 23.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']