Link-Up Issues with DisplayPort IP Core 15.0 Designs - Link-Up Issues with DisplayPort IP Core 15.0 Designs Description The DisplayPort designs (av_sk_4k and sv) in version 15.0 of the DisplayPort IP core has link-up issues on the TX core. This problem is caused by the error in the TX transceiver reconfiguration module link rate connection. The TX transceiver reconfiguration module link rate is connected to the wrong link rate indicator causing the TX transceiver to reconfigure the wrong data rate. Resolution To correct the connection error, edit the following lines in the top wrapper files, top.v for av_sk_4k and sv_dp_demo.v for sv: <Original> bitec_reconfig_alt_av/sv bitec_reconfig_alt_av/sv_i( .tx_link_rate (dp_rx_reconfig_link_rate_8bits), ) <Change to> bitec_reconfig_alt_av/sv bitec_reconfig_alt_av/sv_i( .tx_link_rate (dp_tx_reconfig_link_rate_8bits), ) This issue is fixed in version 15.0 Update 2 of the DisplayPort IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 15.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']