Why do I see timing violations when using the Arria V 10GBaseR PHY soft PCS? - Why do I see timing violations when using the Arria V 10GBaseR PHY soft PCS? Description Due to a problem in Quartus® II software version 13.0 you may see setup or hold timing violations in the soft PCS logic when using the Arria® V device 10GBaseR PHY. This is due to the PMA clock promotion to a Global Clock Network which introduces clock skew. Resolution To fix the timing violations, you can add the following QSF assignments to your design. set_instance_assignment -name GLOBAL_SIGNAL "PERIPHERY CLOCK" -to *altera_xcvr_10gbaser*av_rx_pma|clkdivrx set_instance_assignment -name GLOBAL_SIGNAL "PERIPHERY CLOCK" -to *altera_xcvr_10gbaser*av_tx_pma|clkdivtx This problem will be fixed in a future version of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Basic Functions Clocks (Primary)'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® V FPGAs and SoCs', 'Arria® V GT FPGA'] ['novalue'] ['novalue'] ['novalue']