Are there any problems in the ASMI Parallel II Intel® FPGA IP User Guide? - Are there any problems in the ASMI Parallel II Intel® FPGA IP User Guide? Description Yes. There are some incorrect port names, an incorrect note, and some missing ports. (1) There are the following ports in Figure 1 and Table 2: qspi_dataout (Figure 1) , fqspi_dataout (Table 2) qspi_dclk qspi_scein avl_csr_addr avl_csr_rddata avl_csr_rddata_valid avl_mem_addr avl_mem_rddata_valid avl_mem_byteenble But these are incorrect. The correct port names are as follows: qspi_pins_data qspi_pins_dclk qspi_pins_ncs avl_csr_address avl_csr_readdata avl_csr_readdatavalid avl_mem_address avl_mem_readdatavalid avl_mem_byteenable (2) There is note 3 for Conduit Interface in Table 2, which says, "Available when you enable the Disable dedicated Active Serial interface parameter." But it is incorrect. The correct description is "Available when you enable the Enable SPI pins interface parameter." (3) There are the following missing ports in Table 2: Signal Width Direction Description atom_ports_dclk 1 Output Connects to dclk of ASMI Block atom_ports_ncs 1 ~ 3 Output Connects sce of ASMI Block atom_ports_oe 1 Output Connects to oe of ASMI Block atom_ports_dataout 4 Output The atom_ports_dataout outputs the data to the AS data pin through the ASMI Block. For Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V, connects atom_ports_dataout[0:3] to data0out, data1out, data2out, data3out of ASMI Block. For Intel® Cyclone® 10 LP, Cyclone®IV GX, Cyclone®IV E, Stratix® IV, Arria® II, Arria® II GZ, connects atom_ports_dataout[0] to sdoin of ASMI Block. atom_ports_dataoe 4 Output Connects atom_ports_dataoe[0:3] to data0oe, data1oe, data2oe, data3oe of ASMI Block atom_ports_datain 4 Input The atom_ports_datain receives the data from the AS data pin through the ASMI Block. For Intel® Arria® 10, Cyclone®10 GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V, connects atom_ports_datain[0:3] to data0in, data1in, data2in, data3in of ASMI Block. For Intel® Cyclone® 10 LP, Cyclone® IV GX, Cyclone® IV E, Stratix® IV, Arria® II, Arria® II GZ, connects atom_ports_datain[1] to data0out of ASMI Block. Resolution These ports are available when you enable the Disable dedicated Active Serial interface parameter. Custom Fields values: ['novalue'] Troubleshooting 14019896738 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] novalue 22.1 ['Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'MAX® 10 10 FPGAs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']