Is there an issue with sharing OCT between master and slave UniPHY based controller IPs for Stratix V RLDRAMII and QDRII? - Is there an issue with sharing OCT between master and slave UniPHY based controller IPs for Stratix V RLDRAMII and QDRII? Description Yes, there is an issue with sharing OCT between master and slave UniPHY based controller IPs for Stratix® V RLDRAMII and QDRII in Quartus® II software versions 11.0 and 11.0SP1. In order to share the OCT between a master and a slave UniPHY based controller, you will have to manually make “Termination Control Block” assignment to the slave interface pins with calibrated On Chip Termination assignments associating them with the master OCT block. To make the assignment: 1. Open the assignment editor in Quartus II software. 2. Add all the slave signal using output and input terminations with calibrations. 3. Select the Assignment Name as “Termination Control Block” and for Value tab find the Termination Control Block module in master module. Find the instance name as *uoct_control|sd1a_0* by node finder. This issue will be fixed in a future version of the Quartus II software. Related Articles What files do I need to update in my UniPHY controller when OCT sharing is enabled? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']