Why does the EMIF calibration hang when both an Intel® Arria® 10 External Memory Interfaces IP and an Intel Arria 10 PHYLite IP are placed in the same I/O column? - Why does the EMIF calibration hang when both an Intel® Arria® 10 External Memory Interfaces IP and an Intel Arria 10 PHYLite IP are placed in the same I/O column?
Description Both the local_cal_fail signal and the local_cal_success signal may not assert high after EMIF calibration when both an Intel® Arria® 10 EMIF IP and an Intel Arria 10 PHYLite IP with dynamic reconfiguration enabled are placed in the same I/O column. Resolution This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Software.
Custom Fields values:
['novalue']
Troubleshooting
FB: 546929;
False
['External Memory Interfaces Arria® 10 FPGA IP', 'PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP']
['FPGA Dev Tools Quartus® Prime Software Pro']
18.1.1
16.0
['Arria® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2023-01-15
external_document