Why are the signals in the Signal Tap Logic Analyzer which are actually connected displayed in red? - Why are the signals in the Signal Tap Logic Analyzer which are actually connected displayed in red? Description Due to a problem in the Quartus® Prime Pro Edition Software version 18.1 and earlier, the signals in the Signal Tap Logic Analyzer may be displayed in red, even though they are actually connected to the internal nodes during compilation. Resolution To check whether the signals in the Signal Tap Logic Analyzer are correctly connected, go to the Compilation Report > Synthesis folder > In-System Debugging report. The actual connection column reports the real connection after compilation. This problem is fixed starting with the Quartus® Prime Pro Edition Software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1507116293 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']