Advanced System Design Using Platform Designer: System Optimization - Click the ENROLL button near the top of the screen to play this eLearning. 46 Minutes This training is part 3 of 4. The Platform Designer system integration tool saves significant time by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. In this training you will learn about some advanced capabilities of the tool. In the third part, you will learn about how Platform Designer builds its interconnect for your unique design and why the generated results might not always meet timing or performance requirements. Platform Designer automatically adds adapters to allow different components to communicate with each other, and these adapters may affect timing in the system. You'll learn techniques you can use to improve system performance, from standard interface design to the addition of pipeline bridges. Course Objectives At course completion, you will be able to: Understand why and how timing issues can occur in Platform Designer systems Use techniques to improve system performance Implement changes in a system's topology through the addition of pipeline bridges that can help close timing Skills Required Background in digital logic design Familiarity with the Altera® Quartus® Prime software Familiarity with the Platform Designer system design tool If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (cc) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OAQSYSOPT. FPGA_OAQSYSOPT. <p>Advanced System Design Using Platform Designer: System Optimization</p>