Why does Intel® Stratix ® 10 Avalon®-ST Interface for PCI Express* IP show BAR size of 7 bits is supported? - Why does Intel® Stratix ® 10 Avalon®-ST Interface for PCI Express* IP show BAR size of 7 bits is supported? Description Due to incorrect rule check in the IP GUI, Intel® Stratix ® 10 Avalon®-ST Interface for PCI Express* IP for Intel® Quartus® Prime Pro 19.3 and earlier allows minimum BAR size of 7 bits to be selected. However, this selection will still show FPGA advertising 8 bits of BAR size. The minimum BAR size supported is 8 bits. Resolution This problem is fixed in Intel® Quartus® Prime Pro software version 19.4. Custom Fields values: ['novalue'] Troubleshooting 1507412456 False ['Avalon-ST Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.4 19.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']