Dedicated Clock Pins for MAX 10 - Dedicated Clock Pins for MAX 10 Hello Intel Community, I am currently designing a system using the Intel MAX 10 FPGA, specifically the 10M02SCM153C8G in the compact M153 micro-package. Due to the highly constrained pin resources and the presence of only a single hardware PLL (PLL1) on this device, I need to ensure that my clock network architecture conforms strictly to the hardware requirements to achieve optimal jitter performance and complete phase compensation. My Application Topology: Clock Input: An external reference clock enters the FPGA and drives the inclk0 port of the instantiated ALTPLL IP core. Phase Shift: Inside the ALTPLL, the clock waveform is inverted by 180 degrees. Clock Distribution: This 180-degree phase-shifted clock is split into two destinations: Internal: It drives an internal single-clock FIFO (scfifo) within the FPGA fabric. External: It is routed out through a physical I/O pin to drive an external MCU. My Questions for Intel Support: Dedicated Input Pins: For the M153 package of the 10M02 device, which physical pin numbers are the true Dedicated Clock Input Pins that are directly hardwired to the internal PLL1's inclk0 port, enabling full hardware-level phase compensation (Normal Mode) without introducing routing delays or Quartus compilation warnings? Dedicated Output Pins: To output the 180-degree inverted clock to the external MCU, does this device feature any Dedicated Clock Output Pins (such as PLL external clock outputs) that are physically bonded out in the M153 package? Or are we required to route this clock out via regular user I/O pins through the global clock network? ALTPLL Operation Mode Advice: Considering that this clock simultaneously drives an internal FIFO and an external MCU, which compensation mode (Normal Mode vs. Zero-Delay Buffer Mode) does Intel recommend for the ALTPLL IP core to minimize clock skew and ensure optimal timing closure? Are there any specific parameters (e.g., compensate_clock) that must be explicitly configured to align with the chosen dedicated pins? Any official documentation snippets, device handbook references, or design guidelines regarding the clock routing constraints for this specific micro-package would be highly appreciated. Thank you in advance for your technical assistance! Best regards, Martin. Replies: Re: Dedicated Clock Pins for MAX 10 Thank you, Frank, for the replies. Hi Martin, Do you have any other questions on top of Frank's reply? Regards, Aqid Replies: Re: Dedicated Clock Pins for MAX 10 Hi Martin, Pin Planner info is correct. Please compare with your previous post that confuses in- and outputs. Only difference is wheter PIN_L1 (outclk_n) can be alternatively used as single ended dedicated clock output. According to Quartus compilation result it can. Regards Frank Replies: Re: Dedicated Clock Pins for MAX 10 Hi Frank, I’m a bit confused now. In the Pin Planner, when I select the PLL1 option in the report, what is the meaning of the pins enclosed by the bold black box? If they do not represent the input and output pins of PLL1, then what are they? After I select the checkbox, it specifically highlights these pins by enclosing them within a bold black box. My application is quite simple, utilizing only an SCFIFO and some integrated peripheral logic circuits. However, if the FPGA has sufficient resources, I would like to optimize its utilization to the best possible state, as I may implement a 50MHz application in the future. Replies: Re: Dedicated Clock Pins for MAX 10 Hi Martin, "Pins J4, J5, K4, and K5 can be used as PLL OUTPUTs. Pin P2 can be used as a PLL INPUT." No and no, it's the other way around. As I mentioned, PIN_N1 is the other dedicated PLL output of 10M02SC153. If you are not obliged to achieve lowest jitter and skew, you can route PLL output to any IO pin and also use other dedicated clock inputs not directly routed to PLL1, e.g. CLK[2,3][p,n]. Regards Frank Replies: Re: Dedicated Clock Pins for MAX 10 Hi Frank, Sorry, I’ve been thinking about this and I still have a few questions. I didn't mention PIN_N1 earlier, and N1 is not used in my design. Alternatively, could you directly clarify if the bold black boxes shown in the Pin Planner interface (with the "Report" option checked on the top left for PLL INPUT and PLL OUTPUT) represent the available PLL pins for this FPGA? For example, based on this diagram: Pins J4, J5, K4, and K5 can be used as PLL OUTPUTs. Pin P2 can be used as a PLL INPUT. Is my understanding correct? Thank you. Replies: Re: Dedicated Clock Pins for MAX 10 Thank you. Replies: Re: Dedicated Clock Pins for MAX 10 Hi Martin, you are correct. PIN_N1 can be additionally used as single ended clock output. CLK[6,7] pins mentioned in my previous post aren't available for 10M02. Regards Frank Replies: Re: Dedicated Clock Pins for MAX 10 Hi Frank. I have a quick question regarding the Pin Planner. If I check these two specific options in the Report panel, do the pins outlined with a thick black box in the Top View represent the actual dedicated pins for PLL1? Replies: Re: Dedicated Clock Pins for MAX 10 Hi Martin, your questions are basically answered in MAX10 Device Handbook and Pinout documents. Your device has only PLL1 (left side) and one pair of dedicated clockout pins. Dedicated input pins for PLL1 are CLK[0,1][p,n] and CLK[6,7][p,n], but not CLK2p pin J12 selected in your design. Also pin K4 is no dedicated clockout pin. Depending on your application, non-dedicated clock routing warnings can be possibly ignored. Regards Frank Replies: Re: Dedicated Clock Pins for MAX 10 Hi, Aqid. I have previously reviewed this documentation, which is why I was careful when selecting the pins. For my design, I selected J12 as the input and K4 as the output, as shown in the image below. However, during compilation, I am still getting the following errors/warnings: Warning (15055): PLL "PLL180:inst2|altpll:altpll_component|PLL180_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input Info (15024): Input port INCLK[0] of node "PLL180:inst2|altpll:altpll_component|PLL180_altpll:auto_generated|pll1" is driven by PIXCLK~inputclkctrl which is OUTCLK output port of Clock control block type node PIXCLK~inputclkctrl Warning (15064): PLL "PLL180:inst2|altpll:altpll_component|PLL180_altpll:auto_generated|pll1" output port clk[0] feeds output pin "PIXCLK_INV~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance Even after checking the datasheet, I still cannot figure out which specific external pins are the dedicated PLL inputs and outputs for this particular part number (10M02SCM153C8G) that would eliminate these warnings. Could you please explicitly point out those exact physical pins for me? The reference material you provided seems to be a general guideline for the entire MAX 10 family, rather than specific to this package(10M02SCM153C8G). Additionally, I would like to ask about the symbols on the pins in the TOP VIEW diagram. There are symbols indicating positive-edge and negative-edge pulses—do these carry a specific technical meaning? In my case, the clock enters through J12 as a negative-edge pulse, and I need to invert it to a positive-edge pulse before passing it to C0 and C1, which is different from the symbol shown on the J12 pin. Replies: Re: Dedicated Clock Pins for MAX 10 Hi Martin, For MAX 10 devices, we recommend driving the PLL input from the dedicated clock input pins (CLK[0..7]p/n). These pins are directly connected to the device clocking resources and are intended for PLL reference clocks. Refer here: https://docs.altera.com/r/docs/683232/current/max-10-fpga-device-family-pin-connection-guidelines/clock-and-pll-pins Regarding the exact physical pin numbers, you can check using the MAX 10 device pinout file or Quartus® Prime Pin Planner for the specific device OPN that you used. Regards, Aqid Replies: Re: Dedicated Clock Pins for MAX 10 Hi, actually I just want to know which specific pins are used by ALTPLL in 10M02SCM153C8G.