Potential Data Corruption on SerialLite III Streaming IP Core Arria 10 Source and Duplex Interface for Lane Rate > 15 Gbps - Potential Data Corruption on SerialLite III Streaming IP Core Arria 10 Source and Duplex Interface for Lane Rate > 15 Gbps Description The SerialLite III Streaming IP core Arria 10 variants for lane rate > 15 Gbps (which uses 64-bit PCS interface) may result in FIFO overrun/underrun condition in the hardened PCS. This is metaframe-specific. When this condition happens, a realignment takes place on the source (Tx) interface and this results in a data corruption on the sink (Rx) interface. This issue is found in Quartus II versions 14.0, 14.1, and 15.0. Resolution Use the metaframe values that are tested below : For ECC disabled mode, use metaframe = 200, 400, 4000 For ECC enabled mode, use metaframe = 400 Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']