Why doesn't the O-RAN Intel® FPGA IP design example support the Aldec Riviera simulator for the Intel Agilex® device F-Tile in the Intel® Quartus® Prime Pro Edition Software v22.4 and earlier ? - Why doesn't the O-RAN Intel® FPGA IP design example support the Aldec Riviera simulator for the Intel Agilex® device F-Tile in the Intel® Quartus® Prime Pro Edition Software v22.4 and earlier ? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v22.4 and earlier, the O-RAN Intel® FPGA IP design example does not support the Aldec Riviera simulator for the Intel Agilex® device (F-Tile). Resolution There is no workaround currently. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 15012609827 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 22.4 ['Agilex™ 7 FPGA F-Series', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']