Arria® 10 GT FPGA Overview - FPGAs enabled with up to 78 full-duplex transceivers with data rates up to 25.78 Gbps chip-to-chip, 12.5 Gbps backplane and up to 1,150K equivalent logic elements (LEs). Product Pages Broadcast Test Wireline Overview At 20nm, Arria 10 GT FPGAs feature higher transceiver performance of up to 25.78 Gbps chip-to-chip and 12.5 Gbps for backplane communication, with up to 1,150K equivalent logic elements. Arria 10 GT FPGA Product Table Benefits Enables high-speed connectivity with integrated transceivers supporting advanced serial protocols, allowing for reliable data transfer in applications such as optical networking, wireless infrastructure, and data communications. High-Speed Transceivers and DSP Processing Provides robust signal integrity and low-latency performance to simplify the design of complex high-bandwidth systems that require consistent throughput and reliable link operation. Flexible Embedded Processing Options Supports advanced clocking and jitter management features, allowing designers to meet demanding interface timing requirements across a variety of high-speed interconnect standards. Power-Efficient Performance for Complex Designs Key Features Support communication transfer speeds of up to 25.78 Gbps between various chips or components within an electronic system. 25.78 Gbps Transceiver Speed DSP blocks with integrated floating-point capabilities provide high-performance computing and can deliver up to 1.5 TeraFLOPs of processing power. Enhanced Floating-Point Capabilities This device offers seven 32-bit DDR4 memory interfaces operating at up to 2,400 Mbps, delivering increased external memory bandwidth,simplifying design,and optimizing memory controller usage. Increased External Memory Bandwidth Applications Optical transport, Ethernet, and protocol bridging Wireline High-speed video transport and processing Broadcast and Pro AV Signal capture and high-speed data analysis Test and Measurement Dev Kits, IP, Example Designs & Software Get Started: Development Kits, IP, Example Designs and Software Dev Kit Find Partner Boards Looking for a development kit? Explore available partner boards to get started. IP Interlaken IP The Interlaken FPGA IP core is Interlaken Protocol Definition v1.2 compliant and allows system developers to achieve high-bandwidth throughput in their systems. O-RAN FPGA IP The IP manages transmission and receiver windows, which you can place relative to the air interface based on predefined or measured transport delay. Example Designs FPGA Developer Site GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral. Example Design Store This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production. Software Quartus® Prime Pro Edition Design Software Quartus® Prime Standard Edition Design Software Documentation Documents Documentation Arria 10 FPGA Product Table Arria 10 Documentation Quick Links Arria 10 GT FPGA Device Overview Arria 10 FPGA Datasheet Support Resources Arria® 10 GT FPGA