Why does rx_ready[i](i>0) of F-tile PMA/FEC Direct PHY FPGA IP tie to 0 when the number of PMA lanes is set to more than one and enabled per PMA lanes TX and RX ready signal? - Why does rx_ready[i](i>0) of F-tile PMA/FEC Direct PHY FPGA IP tie to 0 when the number of PMA lanes is set to more than one and enabled per PMA lanes TX and RX ready signal? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, rx_ready[i](i>0) of F-Tile PMA/FEC Direct PHY FPGA IP tie to 0 when the number of PMA lanes set to more than one and enable per PMA lanes TX and RX ready signal. Resolution To work around this problem in the Quartus® Prime Pro Edition software version 24.1, can monitor rx_lane_current_state[i][1] to instead rx_ready[i](i>0) status. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15016398500 False ['F-Tile PMA/FEC Direct PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']