SHA-3: Secure Hash Crypto Engine - The SHA-3 IP core is a high-throughput, area-efficient hardware accelerator for SHA-3 cryptographic hashing, compliant with NIST FIPS 180-4 and FIPS 202. It operates independently of a host processor… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Stratix® V GS FPGA Stratix® V GX FPGA Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® III FPGA The SHA-3 is a high-throughput, area-efficient hardware accelerator for the SHA-3 cryptographic hashing functions, compliant to NIST’s FIPS 180-4 and FIPS 202 standards. The accelerator core requires no assistance from a host processor and uses standard AMBA® AXI4-Stream interfaces for input and output data. An AXI4-Stream to AXI4 Memory Mapped bridge, with or without DMA capabilities, can be used with the core and is separately available from CAST. A single instance of the core implements all fixed-length and extendable-output hash functions. The cryptographic function, the length of the extendable output function (up to 2GB) is chosen at run time via AXI4-Stream side-band signals and can be different for every input message. The SHA-3 core is also highly configurable at synthesis time, to ease integration in systems with different requirements. The data-bus width of the input and output interfaces is configurable at synthesis time. The number of SHA-3 permutation rounds per clock cycle is also configurable at synthesis time, allowing users to trade throughput for silicon resources. Under its minimum configuration of one permutation per cycle, the core processes 50 bits per cycle depending on the hashing function. Its throughput can scale by implementing 2, 3, or 4 permutations per cycle respectively, enabling throughputs in excess of 100Gbps in modern ASIC technologies. The core is designed for ease of use and integration and adheres to industry-best coding and verification practices. Technology mapping, and timing closure are trouble-free, as the core contains no multi-cycle or false paths, and uses only rising-edge-triggered D-type flip-flops, no tri-states, and a single-clock/reset domain. Filters /Transforms Access Aerospace Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Industrial Medical Test Transportation Wireless SHA-3: Secure Hash Crypto Engine Key Features Supports FIPS 202 SHA-3 and XOF, FIPS 180-4 SHA-3, all fixed-length functions (SHA3-224/256/384/512), SHAKE-128/256, fully NIST-validated. Offering Brief Yes Yes No Yes Encrypted Verilog Encrypted VHDL Verilog VHDL Stratix® V GS FPGA Stratix® V GX FPGA Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® III FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U6qMAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, VHDL, Encrypted VHDL, or FPGA netlist Ordering Information SHA-3 a1JUi0000049U6qMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2025-10-31T21:00:54.000+0000 The SHA-3 IP core is a high-throughput, area-efficient hardware accelerator for SHA-3 cryptographic hashing, compliant with NIST FIPS 180-4 and FIPS 202. It operates independently of a host processor, using AMBA® AXI4-Stream interfaces for input and output. An optional AXI4-Stream to AXI4 Memory Mapped bridge, with or without DMA, can be used. A single core instance implements all fixed-length and extendable-output hash functions, with function and output length (up to 2 GB) selectable at runtime per input message. The core is highly configurable at synthesis, including bus width and SHA-3 permutation rounds per cycle, enabling throughput–area trade-offs. One permutation per cycle processes 50 bits per cycle, scaling to over 100 Gbps with multiple permutations in modern ASICs. Fully synchronous, single-clock, scan-ready, LINT-clean, it uses only rising-edge flip-flops, with no false or multi-cycle paths, simplifying integration and verification. Partner Solutions