Building an Altera® Stratix® 10 FPGA Transceiver PHY Layer - 39 Minutes In the Building an Altera® Stratix® 10 FPGA Transceiver PHY Layer course, you will learn how to define the three resources that make up an Altera® Stratix® 10 FPGA transceiver PHY layer solution, namely, the transceiver PHY, the transceiver PLL and the transceiver reset controller. To do this, you will learn how to configure the IP cores found in the Altera® Quartus® Prime Pro development suite for all three Altera® Stratix® 10 FPGA tile types: L-Tiles, H-Tiles and E-Tiles. You will then learn how to properly connect the cores to construct a custom transceiver PHY solution. Course Objectives At course completion, you will be able to: Configure the Altera® Stratix® 10 FPGA PHY IP cores: Altera® Stratix® 10 FPGA L-Tile/H-Tile Native PHY IP core Altera® Stratix® 10 FPGA E-Tile Native PHY IP core Altera® Stratix® 10 FPGA L-Tile/H-Tile Transceiver ATX PLL IP core Altera® Stratix® 10 FPGA L-Tile/H-Tile fPLL IP core Altera® Stratix® 10 FPGA L-Tile/H-Tile Transceiver CMU PLL IP core Altera® Stratix® 10 FPGA Transceiver PHY Reset Controller IP core Construct a transceiver custom PHY layer using the transceiver PHY IP cores Skills Required Familiarity with FPGA/CPLD design flow Familiarity with FPGA architecture Familiarity with the Altera® Quartus Prime Pro design software Knowledge of Altera® Stratix® 10 FPGA transceiver architecture Familiarity with high-speed interfaces and transmission protocols is helpful, but not required If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OS10XCVRPHY. FPGA_OS10XCVRPHY. <p>Building an Altera Stratix 10 FPGA Transceiver PHY Layer</p>