Arria V and Arria V GT Designs Fail Hold Time Requirements in TimeQuest Timing Analyzer - Arria V and Arria V GT Designs Fail Hold Time Requirements in TimeQuest Timing Analyzer Description This errata affects the Triple-Speed Ethernet MegaCore function. Designs that target Arria V and Arria V GT 24-Channel Design with LVDS I/O fail hold time requirements in TimeQuest Timing Analyzer. This issue affects all design that target Arria V and Arria V GT 24-Channel Design with LVDS I/O. Resolution Perform seed sweeping to pass the hold time requirement.This issue will be fixed in a future version of the Triple-Speed Ethernet MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Ethernet'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']