Why is avl_ready stuck low in my DDR3 UniPHY-based controller in Quartus® II 12.0SP2? - Why is avl_ready stuck low in my DDR3 UniPHY-based controller in Quartus® II 12.0SP2? Description In the Quartus® II software version 12.0SP2, DQS tracking is enabled for DDR3 controllers operating above 533MHz in Stratix® V and 450MHz in Arria® V. When DQS tracking is enabled, a sequencer tracking manager (sequencer_trk_mgr.sv) is created to control the tracking. There is a problem in the sequencer_trk_mgr.sv file where the cfg_num_dqs signal is only 3 bits and can support up to 7 DQS groups. For DDR3 interfaces that are 64-bit (8 DQS groups) or 128-bit (16 DQS groups), the sequencer track manager will lock up, causing the Avalon bus-ready signal avl_ready to be stuck low. Resolution This problem has been fixed in Intel® Quartus® Prime Software version 12.1. Related Articles Why is the EMIF debug toolkit hanging in 12.0SP2? Custom Fields values: ['novalue'] Troubleshooting 1408025856 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.0.2 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']