Why does the F-Tile HDMI Intel® FPGA IP Design Example with Fixed Rate Link (FRL) take so long to compile on Windows? - Why does the F-Tile HDMI Intel® FPGA IP Design Example with Fixed Rate Link (FRL) take so long to compile on Windows? Description Due to a SDC problem in the F-Tile HDMI Intel® FPGA IP Design Example with Fixed Rate Link (FRL) an SDC constraint intended for generating reconfiguration profiles, causes the fitter stage to take a longer time during compilation. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 22.3. Download and install Patch 0.45 from the following links: Version 22.3 Patch 0.45 for Windows (.exe) Version 22.3 Patch 0.45 for Linux (.run) Readme for version 22.3 Patch 0.45 (.txt) A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 22.4. Download and install Patch 0.28 from the following links: Version 22.4 Patch 0.28 for Windows (.exe) Version 22.4 Patch 0.28 for Linux (.run) Readme for version 22.4 Patch 0.28 (.txt) This problem has been fixed starting in version 23.1 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18026217137 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Agilex™ 7 FPGA F-Series'] ['novalue'] ['novalue'] ['novalue']