Why is the 10G Ethernet MAC avalon_st_tx_ready signal de-asserted for at least two clock cycles for each packet streaming? - Why is the 10G Ethernet MAC avalon_st_tx_ready signal de-asserted for at least two clock cycles for each packet streaming? Description The avalon_st_tx_ready signal will be de-asserted for at least two clock cycles for every new packet received on the Avalon® -ST streaming interface. This is necessary for the MAC to perform the following functionality: • Insert preamble and SFD • Insert padding if the frame is short frame. • Insert CRC • Insert End of Frame Delimiter • Insert the right inter packet gap This does not affect the 10G Ethernet MAC throughput. Resolution No workaround or fix is available. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Ethernet'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']