Why doesn't pulsing transceiver edge sensitive input signals have an effect in Cyclone V, Arria V and Stratix V transceiver devices? - Why doesn't pulsing transceiver edge sensitive input signals have an effect in Cyclone V, Arria V and Stratix V transceiver devices? Description When driving the Cyclone® V, Arria® V and Stratix® V device transceiver edge sensitive signals, such as the rx_std_wa_patternalign signal, you must still comply with the minimum pulse width requirement. The minimum typical pulse width is two parallel clock cycles. Resolution Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V SX FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']