How can I reset the bitslip in the ALTLVDS_RX mega function in Arria® V and Cyclone® V devices? - How can I reset the bitslip in the ALTLVDS_RX mega function in Arria® V and Cyclone® V devices? Description The rx_cda_reset input port of the ALTLVDS_RX malfunction is not supported in Arria® V GX, GT, SX, and ST devices and Cyclone® V devices beginning in the Quartus® II software version 12.1. The bitslip, also referred to as the data alignment, is set to the zero latency position (reset) by asserting pll_areset. Note the RTL simulation model does not reset the bitslip when pll_areset is asserted. This is an issue only with the RTL simulation model. The RTL simulation model is scheduled to be fixed in a future version of the Quartus II software. Resolution The bitslip latency will be set to the zero position when pll_areset is asserted in gate level simulation, and in hardware. Custom Fields values: ['novalue'] Troubleshooting 2205726932 False ['Avalon ALTPLL'] ['FPGA Dev Tools Quartus II Software'] 14.1 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']