When using the Ethernet Multirate Intel® FPGA IP with PTP enabled on port 1, why is the RX Timestamp interface signal not aligned with the RX Start of Packet indicator? - When using the Ethernet Multirate Intel® FPGA IP with PTP enabled on port 1, why is the RX Timestamp interface signal not aligned with the RX Start of Packet indicator? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4, the Ethernet Multirate Intel® FPGA IP with PTP enabled on port 1 will not align the RX Timestamp interface signal with the RX Start of Packet indication. This problem affects the following Reconfiguration Group configurations: Client Interface: MAC Avalon Streaming Interface with PTP Enabled PMA Type Reconfig group Operating Ethernet mode profile Affected Interface Signals FGT 100GE-2 Reconfigurable 10/25GE-1 Valid o_p1_ptp_rx_its [95:0] not aligned to o_rx_startofpacket[1] FHT 100GE-2 Reconfigurable 10/25GE-1 Valid o_p1_ptp_rx_its [95:0] not aligned to o_rx_startofpacket[1] Client Interface: MAC Segmented with PTP Enabled PMA Type Reconfig group Operating Ethernet mode profile Affected Interface Signals FGT 100GE-2 Reconfigurable 10/25GE-1 Valid o_p1_ptp_rx_its [95:0] not aligned to SOP on o_rx_mac_inframe[2] FHT 200GE-2 Reconfigurable 50GE-1 Valid o_p1_ptp_rx_its [95:0] not aligned to SOP on o_rx_mac_inframe[5:4] Resolution To work around this problem, you should delay the RX data interface by (5) i_clk_rx clock cycles for the 10/25GE-1 profiles or (2) i_clk_rx clock cycles for the 50GE-1 profile. This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 23.1. Custom Fields values: ['novalue'] Troubleshooting 15012414843,15012434653 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']