VHDL Conditional analysis example - VHDL Conditional analysis example I am experiencing an issue with ip generation in quartus prime pro 25.1. A build stalls when attempting to run either qsys-validate or qsys-generate. Looking in task manager I can see that the JAVA process for these commands has been started but does not appear to be doing anything. It appears to be random on which specific command the build stalls. I have also seen it stall when attempting to generate the debug ip during the synthesis stage I have tried 1 Reinstalling quartus 2 Running on a different computer Neither have successfully resolved the issue. Kind regards, Graeme Replies: Re: VHDL Conditional analysis example Is there any further question? Replies: Re: VHDL Conditional analysis example Kindly check the soln in https://community.altera.com/discussions/quartus-prime/critical-notice-ddm-error--crash-issue-in-quartus%C2%AE-prime-pro-v23-3%E2%80%93v25-3-1-%E2%80%94-act/349761 Replies: Re: VHDL Conditional analysis example I too have observed this phenomenon emerge spontaneously around Jan 11. I believe it is part of the constellation of symptoms, one of the intermittent failure modes, caused by a broadly affecting Quartus Pro bug discussed in the following thread: https://community.altera.com/discussions/quartus-prime/quartus-pro-25-3-crash-using-rhel78/349584/replies/349607 Replies: Re: VHDL Conditional analysis example The issues started for me on the 12th January 2026. Builds which I had previously built without error 9th January no longer build