Why does the R-Tile FPGA IP for Compute Express Link* (CXL*) Type3 Design Example fail at system enumeration in Quartus® Prime Pro Edition Software Version 23.3? - Why does the R-Tile FPGA IP for Compute Express Link* (CXL*) Type3 Design Example fail at system enumeration in Quartus® Prime Pro Edition Software Version 23.3? Description Due to a problem in Quartus® Prime Pro Edition Software version 23.3, you might observe system enumeration failure for R-Tile FPGA IP for Compute Express Link* (CXL*) Type3 Design Example when using "lspci | grep 0ddb" in Linux command line. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.4. Custom Fields values: ['novalue'] Troubleshooting 15014946780 False ['R-Tile for Compute Express Link Solution'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 23.3 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']