Why is the read data value incorrect for the DQS input delay when using the Dynamic Reconfiguration mode in the Arria® 10 PHYLite IP? - Why is the read data value incorrect for the DQS input delay when using the Dynamic Reconfiguration mode in the Arria® 10 PHYLite IP? Description When using the Dynamic Reconfiguration mode in the Arria® 10 PHYLite IP, you may write a value for the DQS input delay to a specific address location, however, you may see a different data value for the DQS input delay when reading back from that specific location because the legal range of the DQS input delay isn’t fixed and is dependent on the VCO frequency. Resolution A typical calibration methodology is to sweep the DQS input delay for pass/fail results. An expected calibration is to increment the DQS Input delay through a valid range and capture the largest value before it passes. Then continue to increment the DQS input delay and capture the smallest value before it fails. The DQS input delay is then set to the mid-point of the above two values. However, the entire 10-bit range value for the DQS input delay (i.e. 0X3FF) won’t be available for slower interface frequencies because there exists only a limited number of delay cells where each cell has a Process, Voltage, and Temperature (PVT) dependent fixed delay value. The Arria® 10 PHYLite circuit caps the DQS Input delay to a legal maximum value. Therefore, if you write a value for the DQS input delay greater than the maximum DQS input delay, then you will actually write a value equal to the maximum DQS input delay and you will read back a value equal to the maximum DQS input delay. Below is a table showing some select Arria® 10 PHYLite clock frequencies and the maximum DQS input delay. Interface Clock Frequency (MHz) VCO Frequency User Clock Rate Maximum DQS Input Delay 133 533.33 Full-rate (FR) 0x0FD 160 640 FR 0x23F 160 320 Half-rate (HR) 0x100 320 320 HR 0x0FD 320 640 Quarter-rate (QR) 0x23D 640 640 QR 0x23F 960 960 QR 0x352 1200 1200 QR 0x3FF Note: The maximum DQS input delays differ as they depend on the device Process, Voltage, and Temperature (PVT). Custom Fields values: ['novalue'] Troubleshooting 1409507314 True ['PHY Lite for Parallel Interfaces Arria® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.0.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']