Why are GTS transceiver tests including PCIe* enumeration failing on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1)? - Why are GTS transceiver tests including PCIe* enumeration failing on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1)? Description Due to a change in the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1) manufacturing test process, some boards have a corrupted FPGA image stored in the FPGA QSPI flash. This corrupt image results in failures in transceiver operation even if a new image is loaded via JTAG. Examples of issues include failure of the PCIe* to enumerate and SFP transceiver loopback tests failing. Resolution To fix this problem, follow these steps Ensure that the MAX® 10 FPGA POF image is updated as described in this KDB: Why does the GTS AXI Streaming IP for PCI Express* design example for Agilex™ 5 FPGAs fail to operate and enumerate in hardware when loaded from QSPI on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1)? Download ghrd_a5ed065bb32ae6sr0_hps.jic to a host computer with the Quartus® Prime Pro Edition Programmer v25.3 or newer to update the Agilex™ 5 FPGA E-Series 065B Modular Development Kit FPGA QSPI flash. Set the Agilex™ 5 FPGA Modular Development Kit carrier board switch S13-3 and S13-4 to "OFF" so the USB JTAG option is selected and the Agilex™ 5 FPGA is on the JTAG chain. See switch setting in this photo: Connect the micro USB cable to the Agilex™ 5 FPGA Modular Development kit front panel JTAG connector (J35) and attach other end to host computer. Bring up the Quartus® Prime Pro Edition (25.3 or newer) Programmer GUI, select "Auto Detect" . Your display should be similar to the one shown below: Select the A5EC065BB32 device, right click and change file to ghrd_a5ed065bb32ae6sr0_hps.jic. Select "Program/Configure" and "Verify" for the MT25QU02G device as shown below: Click "Start" to begin the programming process. The programming process takes approximately 5 minutes to complete. Power cycle the board for the new image to be loaded. This manufacturing problem is resolved in production versions of the Agilex™ 5 FPGA Modular Development Kit. Custom Fields values: ['novalue'] Troubleshooting 14026136598 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['Agilex™ 5 FPGA E-Series 065B Modular Dev Kit (ES)']