Why does the Avalon® controller in the design example generate the wrong write address to the Intel® Arria®10 PHYLite IP which causes the dynamic reconfiguration to fail? - Why does the Avalon® controller in the design example generate the wrong write address to the Intel® Arria®10 PHYLite IP which causes the dynamic reconfiguration to fail? Description The wrong address offset is generated when using the Intel® Arria® 10 PHYLite design example with an Avalon® controller. Resolution This problem is scheduled to be fixed in a future release of the Intel Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting 553654 False ['PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 16.0 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']