Designing with the 28-nm Hard IP for PCI Express - 17 Minutes In this class, you will learn rules that must be followed in order to ensure proper placement of Hard IP for PCI Express® blocks and transceiver channels within your target Cyclone® V, Arria® V or Stratix® FPGA, failure of which can lead to compilation errors and possibly board re-spins. You will learn how to select the best clock resource based on location and PCI Express lane speed and configuration. You will also learn debugging tools and techniques to employ when bringing up your PCIe link in a system. Targeted devices: Cyclone® V, Arria® V, and Stratix® V FPGAs Course Objectives At course completion, you will be able to: Avoid board-level issues when choosing locations for Hard IP for PCI Express transceiver channels Selecting the right PLL for low-jitter transmit operation Describe the tools and techniques used to debug a Hard IP design Skills Required Some understanding of the PCI Express Protocol specification is helpful, but not required Familiarity with common high-speed transceiver architecture or viewing the following transceiver basics course or attending the Building Gigabit interfaces in Altera® transceiver devices Familiarity with FPGA/CPLD design flow Familiarity with the Quartus design software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OPCIDESIGN. FPGA_OPCIDESIGN. <p>Designing with the 28-nm Hard IP for PCI Express</p>