Agilex™ 7 SoC FPGA Hard Processor System (HPS) Overview - 15 Minutes In this training you will learn about the architecture of the Agilex™ 7 SoC FPGA. You will learn about the Hard Processor System (HPS) and its contents. We begin by discussing the ARM* Cortex*-A53 MPU (Multi-Processor Unit). The Cache Coherency Unit (CCU) and System MMU (SMMU) memory management blocks are explained next. The bridges between the HPS, FPGA, and SDRAM are also discussed. The peripherals of the HPS are discussed including: UART, I2C, DMA, Ethernet MAC, and USB. *Other names and brands may be claimed as the property of others. Course Objectives At course completion, you will be able to: Understand the architecture of the Agilex™ 7 SoC FPGA HPS Understand the CCU and SMMU memory management blocks List the bridges available in the Agilex™ 7 SoC FPGA List the blocks of the HPS in the Agilex™ 7 SoC FPGA Skills Required Basic knowledge of computer architecture If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OEMBAGIL. FPGA_OEMBAGIL. <p>Agilex 7 SoC FPGA Hard Processor System (HPS) Overview</p>