When does PCIe core assert and deassert TxsWaitRequest_o? - When does PCIe core assert and deassert TxsWaitRequest_o? Description By design, PCIe ® core sets active high TxsWaitRequest_o to high after it is out of reset. However, application logic should only monitor TxsWaitRequest_o when it asserts TxsRead_i or TxsWrite_i. The reason TXsWaitRequest_0 is asserted by default because the core may need additional cycles to decode the TX command transmitted by application layer. This process begins when TxsRead_i or TxsWrite_i is active. 1. There are two reasons why the core needs the extra latency: a. To perform address translation for Avalon ® -MM to PCI Express ® request b. To break the Write transaction to multiple requests as required by the PCI Express Spec 2. If a TX request is active, the core will eventually clear TxsWaitRequest_o when it is ready to process the next write data or a new command. 3. The core may deassert TxsWaitRequest_o at the same cycle of the request if the core is ready. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Cyclone® IV GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']