JESD204B IP Core TX Soft PCS Outputs All Zero Parallel Data During Reset State - JESD204B IP Core TX Soft PCS Outputs All Zero Parallel Data During Reset State Description When you select Enable Soft PCS for the PCS option parameter, the TX soft PCS outputs all zero during the reset state. Therefore, the deterministic latency for Subclass 1 mode is inconsistent. This issue does not impact the functionality of the CDR at the receiver side because the data going into the CDR is not DC-balanced. This issue affects the JESD204B IP core in Quartus II software version 14.0. Resolution None. This issue will be fixed in a future version of the JESD204B IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']