Why does my Avalon® Memory Mapped register access to the F-tile Ethernet Intel® FPGA Hard IP fail to complete? - Why does my Avalon® Memory Mapped register access to the F-tile Ethernet Intel® FPGA Hard IP fail to complete? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, Avalon® Memory Mapped register accesses to the F-tile Ethernet Intel® FPGA Hard IP will fail to complete if the access is made to an address outside of the ranges defined in the user guide. In such a situation, you will see that the “waitrequest” signal fails to de-assert. Resolution There is no workaround for this problem. You should ensure that all register accesses are performed on legal address spaces. This problem will be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16020013032 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 23.1 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']