Fatal Error: Segment Violation: faulting address=(nil), PC=0x7fffef9076bc : 0x7fffef9076bc: db_cdb_sgate!CDB_SGATE_NODE::get_string_hpath(std::__cxx11::basic_string, std::allocator - Fatal Error: Segment Violation: faulting address=(nil), PC=0x7fffef9076bc : 0x7fffef9076bc: db_cdb_sgate!CDB_SGATE_NODE::get_string_hpath(std::__cxx11::basic_string, std::allocator Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, you might see the error message at Analysis & Synthesis stage when using the inference-flow for Tensor-Mode DSPs with RTL that has too many pipeline stages between the result of the intermediate multipliers and their column addition, but otherwise has the correct structure for a tensor-mode DSPs. Resolution To work around this problem, fix the RTL to match the actual tensor mode operation, refer to the templates that are included in the Quartus® Prime Pro Edition Software, as shown below: This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.3. Custom Fields values: ['novalue'] Troubleshooting 15016225723 False ['Native AI Optimized DSP IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']