Why does the Intel® Arria® 10 FPGA PCIe Hard IP treat nullified TLPs (including posted TLPs and non-posted TLPs) as correctable error and set the correctable error register? - Why does the Intel® Arria® 10 FPGA PCIe Hard IP treat nullified TLPs (including posted TLPs and non-posted TLPs) as correctable error and set the correctable error register? Description According to the PCIe specification, when a PCIe physical layer receives nullified TLPs (including posted and non-posted TLPs), it should discard the nullified TLPs and free any storage allocated for these TLPs. Due to a problem with the Intel® Arria® 10 FPGA PCIe Hard IP, when it receives nullified TLPs, it treats them as correctable error and sets the correctable error register. Resolution No workaround for this problem exists. The user application should be aware of the limitation and take care of this scenarios. If correctable errors are reported by the Intel® Arria® 10 FPGA PCIe* Hard IP, the user application can ignore these if they are caused by nullified packets. Typically nullified packets are only utilized in PCIe Switch applications. This problem will not be fixed in a future release of the Intel® Quartus® Prime Software. Custom Fields values: ['novalue'] Troubleshooting FB: 571646; True ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.0 ['Arria® 10 FPGAs and SoCs', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']