PLL Master Required for Simulation of PLL Slave for UniPHY External Memory Interfaces - PLL Master Required for Simulation of PLL Slave for UniPHY External Memory Interfaces Description The example simulation design (generated in the <variation_name>_example_design\simulation folder) does not function correctly if the core is parameterized with PLL Sharing Mode = Slave , DLL Sharing Mode = Slave , or OCT Sharing Mode = Slave. Resolution The workaround for this issue is to ensure that a master instantiation is provided to drive the slave. To do this, follow these steps (a PLL example is shown): Generate a second, identically parameterized, IP core with PLL Sharing Mode set to Master . Manually instantiate the second IP core in the top-level file of the slave core’s example design, <variation_name>_example_design\simulation<variation_name>_example_sim.v . Connect the master and slave by following the usual PLL sharing flow. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PLL'] ['FPGA Dev Tools Quartus II Software'] 11.1 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']