XIP7013E: IPSEC AES-256-GCM - IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s Ipsec extreme speed IP core enhances secure communication at layer three … Xiphera designs and implements hardware-based security using proven cryptographic algorithms. Our strong cryptographic expertise and extensive experience in digital system design enable us to help… Arria® 10 SX FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Stratix® III FPGA IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s Ipsec extreme speed IP core enhances secure communication at layer three (Network) of the OSI model, ensuring the authenticity and confidentiality of data traffic with up to 400G linerates. It leverages the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with a 256-bit key length, for Encapsulating Security Payload (ESP) frame processing within the IPsec protocol. Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Defense Government Medical Test Transportation Wireless XIP7013E: IPSEC AES-256-GCM Key Features Performance: The extreme-speed XIP7013E achieves a throughput exceeding 200 Gbps in modern high-end FPGAs and ASICs. Importantly, XIP7013E does not require any extra interpacket gap cycles even when it processes short packets. The latency of XIP7013E is f ixed, and it does not depend on the length of the input packet. Offering Brief Yes No No Yes Encrypted Verilog Verilog Arria® 10 SX FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Stratix® III FPGA Yes Yes 25.1.1 Offering Brief Production a1JUi0000049UTAMA2 What's Included Encrypted RTL or source code Ordering Information XIP7013E a1JUi0000049UTAMA2 Production Intellectual Property (IP) a1MUi00000BO8toMAD a1MUi00000BO8toMAD Select 2026-04-21T12:58:33.000+0000 IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s Ipsec extreme speed IP core enhances secure communication at layer three (Network) of the OSI model, ensuring the authenticity and confidentiality of data traffic with up to 400G linerates. Partner Solutions