Default start/busy Interface - Default start/busy Interface Hi everyone, I´m trying to understand how the default interface with start, done, busy and stall signals work. Is there any documentation, where i can read more about this? Specifically, if i want to integrate a hls compiled component into a system, what effect will setting the variables to 0 or 1 have? I would guess something like: Invoke the component when start is 1 and busy is 0, returndata is valid when done is 1, dont return done = 1 when stall is 1. Is reset active high? Thanks in advance! Replies: Re: Default start/busy Interface I found this video, which answers the question: https://www.youtube.com/watch?v=aZYBlkcoj8Q&t=483s&ab_channel=IntelFPGA