How do I set different video patterns in the SDI II Intel® FPGA IP design example testbench? - How do I set different video patterns in the SDI II Intel® FPGA IP design example testbench? Description By default in testbench tb_top.v, TEST_RECONFIG_SEQ is set to "half." The video pattern will be reconfigured in the sequence of 12GA-->6GB-->3GA-->HS-->SD. This shows an excellent example of reconfiguration but gives too short a time to detail transmits video data pattern for mode. Resolution Modify the TEST_RECONFIG_SEQ parameter to set different video patterns in the simulation. For example, change it to "12GA" to run a simulation of a 12G video bitstream. This parameter supports multiple options, "full", ''half', "12GA".. etc. Refer to tb_tasks.v for detailed parameter values. Custom Fields values: ['novalue'] Troubleshooting 1508306011 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']