DisplayPort Receiver Performs Link Training Optimization During PHY CTS - DisplayPort Receiver Performs Link Training Optimization During PHY CTS Description When the GPU is not used, the DisplayPort IP core receiver performs link training optimization during physical layer (PHY) CTS. This issue may cause the PHY CTS testing to fail. Resolution To avoid this issue, turn on Enable GPU control. This issue is fixed in version 14.1 of the DisplayPort IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.1 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']