Error: (vopt-3373) Range of part-select [3:4] into 'data_out' [3:0] is reversed - Error: (vopt-3373) Range of part-select [3:4] into 'data_out' [3:0] is reversed Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.3 and earlier, you might see the following error message during the PHY Lite for Parallel Interfaces IP example design simulation with the pin width set to 4. Error: ../../ip/ed_sim/ed_sim_mem_0/altera_phylite_agent_191/sim/phylite_agent.sv(260): (vopt-3373) Range of part-select [3:4] into 'data_out' [3:0] is reversed. # ** Error (suppressible): ../../ip/ed_sim/ed_sim_mem_0/altera_phylite_agent_191/sim/phylite_agent.sv(260): (vopt-2957) LSB 4 of part-select into 'data_out' is out of bounds. Resolution Currently, no workaround exists for this problem. Pin widths of 4 or less show this problem, but pin widths of 5 will work. Custom Fields values: ['novalue'] Troubleshooting 15012012794 False ['PHY Lite for Parallel Interfaces Arria® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 22.3 ['Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']