Why does the Low Latency Ethernet 10G MAC Intel® FPGA IP ignore sequential XON requests when implemented with Priority-based Flow Control (PFC) queues? - Why does the Low Latency Ethernet 10G MAC Intel® FPGA IP ignore sequential XON requests when implemented with Priority-based Flow Control (PFC) queues? Description Due to a problem with the Intel® Quartus® Prime Software version 18.0.1 and earlier, the Low Latency Ethernet 10G MAC Intel® FPGA IP only accepts the first XON request when implemented with Priority-Based Flow Control (PFC) queues. All subsequent XON requests will be ignored and the remaining paused queues will stay paused until the pause quanta expire or become zero. Resolution To work around this problem, have all the paused queues resume simultaneously through a single XON or wait for the pause quanta expiry for the remaining paused priority queues. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.1. Custom Fields values: ['novalue'] Troubleshooting FB: 587132; True ['IP Low Latency 10-Gbps Ethernet MAC and PHY Function IP-10GEUMAC'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 18.0 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']